Single-sided PCBs are the right choice for simple, low-cost applications; double-sided PCBs suit moderate complexity with budget constraints; and multilayer PCBs are essential for high-density, high-speed, or noise-sensitive designs. These three PCB types represent a progression in manufacturing complexity, capability, and cost—each with a clearly defined set of applications where it delivers the best outcome. A single-sided board that costs $0.50 to produce is the correct engineering and commercial decision for a basic LED controller; that same board would be an impractical starting point for a 5G modem. Understanding the structural, electrical, and manufacturing differences between these three categories is the foundation for making sound PCB decisions from the earliest design stage.
A printed circuit board is a laminated structure of conductive copper layers separated by insulating substrate material—most commonly FR4 glass-epoxy laminate. The number of copper layers determines how many independent routing channels exist within the board, which in turn governs routing density, signal integrity, power distribution quality, and electromagnetic compatibility (EMC) performance.
The three fundamental layer configurations each represent a distinct engineering capability tier:
All three PCB types use the same base substrate options, though material selection becomes more critical as layer count increases. FR4 (glass-reinforced epoxy, Tg 130–170°C) is the standard for the majority of commercial and industrial applications. High-frequency designs above 1 GHz increasingly require low-loss laminates such as Rogers 4003C (dielectric constant εr = 3.55, loss tangent 0.0027) or Isola IS680 to maintain signal integrity across multiple layers—a consideration that does not arise in most single-sided applications.
A single-sided PCB has one layer of copper foil bonded to one face of the insulating substrate. Components are typically mounted on the copper side (for through-hole components, lead wires pass through the board and are soldered on the copper side) or on the bare substrate side with SMD components soldered to copper pads on the opposite face.

Single-sided boards are manufactured by a straightforward subtractive process: copper-clad substrate is coated with photoresist, exposed through a circuit pattern film, developed, and etched to remove unwanted copper. The absence of through-hole plating, inner layer lamination, and multiple alignment operations makes single-sided PCBs the simplest and cheapest PCB type to manufacture.
In high-volume production (100,000+ units), a standard single-sided FR4 board measuring 100 × 80 mm can be produced for $0.10–$0.50 per unit. This cost advantage is significant for consumer electronics with tight bill-of-materials targets.
The fundamental constraint of single-sided design is that traces cannot cross without a jumper wire or zero-ohm resistor—there is no second layer to route over an existing trace. This limits circuit complexity to designs where all connections can be routed in a non-crossing planar configuration. Practical upper limits for single-sided designs are typically:
Single-sided boards remain in high-volume production across a range of well-established applications:
A double-sided PCB adds a second copper layer on the opposite face of the substrate and connects the two layers through plated-through holes (PTH)—copper-lined drill holes that create electrical connections between top and bottom copper layers. This single addition fundamentally changes the design space available to the engineer.

PTH vias are drilled through the full board thickness and then electroplated with copper to a wall thickness of 25 µm minimum per IPC-6012 Class 2 (standard commercial) or 20 µm minimum per Class 1. The plating creates a reliable electrical and mechanical connection between layers. Via drill diameters in standard double-sided fabrication range from 0.2 mm to 6.3 mm, with finished hole sizes 0.1–0.15 mm smaller than the drill diameter after plating.
The addition of PTH manufacturing adds chemical copper deposition, electroplating, and additional inspection steps to the fabrication process—increasing unit cost by approximately 30–60% over single-sided at equivalent board size and volume, but providing roughly double the routing capacity.
Multilayer PCBs achieve capabilities that are fundamentally inaccessible to single or double-sided designs—not merely through additional routing capacity, but through qualitatively different electrical performance enabled by internal ground planes, power planes, and controlled differential pair routing in a shielded environment.

Multilayer fabrication begins with individual double-sided inner layer cores, each processed like a standalone double-sided board (image, etch, inspect). The inner layers are then aligned using precision registration pins and laminated together with prepreg (pre-impregnated glass-fiber epoxy) bonding layers in a heated hydraulic press at 170–200°C and 250–400 psi. After lamination, the outer layers are processed, drilling and PTH plating connect all layers, and the board is finished.
Layer-to-layer registration accuracy in high-quality multilayer fabrication is typically ±75–100 µm, ensuring that via drill locations align with copper pads on all internal layers. Advanced fabrication with laser-drilled microvias achieves registration within ±25 µm for HDI (High Density Interconnect) boards.
Dedicating internal layers to solid copper power and ground planes provides three critical benefits that cannot be replicated in two-layer designs:
The arrangement of signal, power, and ground layers within a multilayer stack-up determines the electrical performance of the board. Poor stack-up design negates the advantages of additional layers; good stack-up design maximizes signal integrity and PDN performance within the minimum layer count.
| Layer Count | Layer 1 | Layer 2 | Layer 3 | Layer 4 | Layers 5–N |
|---|---|---|---|---|---|
| 4-layer | Signal (top) | Ground plane | Power plane | Signal (bottom) | — |
| 6-layer | Signal (top) | Ground plane | Signal (inner) | Power plane | Ground plane / Signal (bottom) |
| 8-layer | Signal (top) | Ground plane | Signal (inner 1) | Power plane | Ground / Signal / Power / Signal (bottom) |
Standard through-hole vias in multilayer boards consume pad and anti-pad space on every layer they pass through, even layers they do not connect. In high-density designs with fine-pitch BGA components (0.4–0.5 mm pitch), through-hole vias consume too much routing space. Blind vias (connecting outer to inner layers only) and buried vias (connecting inner layers without reaching the outer surface) allow fan-out routing under BGAs that through-hole vias cannot achieve. These technologies add 30–80% to fabrication cost but are essential for modern high-density processor and memory routing.
| Parameter | Single-Sided PCB | Double-Sided PCB | Multilayer PCB |
|---|---|---|---|
| Copper layers | 1 | 2 | 4–50+ |
| Routing density | Low | Moderate | High to very high |
| Controlled impedance | Not practical | Limited (<200 MHz) | Full support (GHz range) |
| Dedicated power/ground planes | No | Partial | Yes (full internal planes) |
| EMI performance | Poor | Moderate | Good to excellent |
| Relative fabrication cost | 1× (baseline) | 1.3–1.6× | 2×–8× (4 to 12 layers) |
| Design complexity supported | Simple circuits | Moderate complexity | High-speed, dense, mixed-signal |
| Lead time (prototype) | 24–48 hours | 24–72 hours | 3–7 days (4L); 5–14 days (8L+) |
The decision framework for PCB type selection should work through a series of design constraints in order of priority. Cost optimization is only valid after functional requirements are confirmed to be met—selecting a single-sided board to save cost and then discovering that the routing is impossible wastes more time and money than the initial saving.
A common misconception is that choosing a lower layer count always reduces total project cost. In practice, the additional engineering time spent routing a dense design on too few layers, the board area increase required to resolve routing conflicts, and the EMC re-testing costs from a failed certification run frequently exceed the fabrication cost difference between a 2-layer and 4-layer board. A 4-layer board costs approximately 2–2.5× more than a 2-layer board at prototype quantities—often a difference of $30–$80 per board—but avoiding one EMC test cycle saves $5,000–$20,000 in laboratory fees and engineering time.
Understanding the minimum feature sizes achievable on each PCB type helps designers avoid specifying dimensions that exceed their chosen fabricator's capability—a common cause of prototype delays and unexpected cost increases.
| Design Parameter | Single-Sided PCB | Double-Sided PCB | Multilayer PCB (std.) | Multilayer HDI |
|---|---|---|---|---|
| Min. trace width | 0.20 mm | 0.15 mm | 0.10 mm | 0.075 mm |
| Min. trace spacing | 0.20 mm | 0.15 mm | 0.10 mm | 0.075 mm |
| Min. drill diameter | 0.80 mm (NPTH) | 0.20 mm | 0.20 mm | 0.10 mm (laser) |
| Min. annular ring | N/A | 0.15 mm | 0.10 mm | 0.05 mm |
| Aspect ratio (drill) | N/A | Up to 8:1 | Up to 10:1 | Up to 1:1 (blind) |
Always verify specific design rules with your chosen fabricator before finalizing the layout. Fabricator capabilities vary, and designing to the absolute minimum values above without confirmation increases the risk of yield issues and associated cost penalties. A practical approach is to target 130–150% of the fabricator's stated minimum values for non-critical traces and spaces, reserving minimum-rule features only for areas where they are genuinely necessary.